FAPESP and INTEL publish this Call for Proposals and invite interested researchers, working within public or private Higher Education or Research Institutions in the State of São Paulo, to submit projects under the cooperation agreement between FAPESP and INTEL, under the terms and conditions hereinafter set forth.


Academic research on side-channel resistant security for system-on-a-chip (SoC) devices.


FAPESP and Intel’s corporate University Research Office (URO) invite proposals from researchers in the State of São Paulo in Brazil on side-channel resistant security for lightweight Internet of Things (IoT) devices. IoT devices are expected to proliferate significantly in the coming years and pose unique challenges due to limited hardware resources, energy constraints, cost limitations, low bandwidth, and physical exposure to attackers. Unlimited access to IoT devices, in particular, creates opportunities for attackers to exploit side-channel information in order to obtain cryptographic keys, access-controlled data, or other types of protected information. Intel requests proposals for non-incremental research leading to compelling techniques and technologies that will make future lightweight IoT devices significantly more secure against side channel attacks than the current state-of-the-art.


System-on-a-Chip (SoC) based devices are expected to proliferate significantly in the coming years. One well-known source projects the total number of Internet connected devices globally to reach 25 billion by 2015 and 50 billion by 2020.1 Dramatic increases in SoC-based device technologies will continue to be seen in such fields as

  • Consumer electronics (digital cameras, media players, GPS devices, gaming)
  • Mobile communications (smart phones, feature phones, cellular base stations)
  • Health and medicine (diagnostic equipment, patient monitoring devices, medical imaging)
  • Transportation (vehicle control systems, traffic monitoring and regulation)
  • Energy (smart meters, climate sensors, energy management systems)
  • Security (surveillance and monitoring devices, home alarm systems)
  • Industrial applications (control and monitoring, quality management)
  • Commerce/Retail (supply and merchandise management, point-of-sales devices)

Securing SoC-based devices and their associated data is challenging for a variety of reasons: integration of third party IP modules, physical exposure of devices to attackers, lack of administrative configuration or management, low-cost design and manufacturing requirements, limited hardware resources (processor, memory, storage), and highly constrained power budgets. The focus of this research effort is on the design of security for lightweight SoC devices that is resistant to side-channel attacks.

Broadly, a side-channel attack refers to the use of physically observable characteristics of a system or device to deduce internal states and gain access to protected information (e.g., cryptographic keys). Examples of side-channel information that may be exploited to mount such an attack include:

- Variations in execution time,
- Variations in power consumption,
- Variations in electro-magnetic emanation,
- Variations in acoustic behavior, and
- Unexpected behavior caused by induced faults on the device or system.

A canonical side-channel attack may examine side-channel information in a fine-grained and/or statistical manner to study the behavior of a system as it executes a particular instruction, a sensitive operation, or even an entire algorithm. Correlations between system behavior and input data are explored to look for information leaks in the underlying system. Such leaks may reveal a targeted secret directly, supply intermediate data within the underlying computation, or provide clues about the underlying structure or format of computation. Side-channel information often has the effect of reducing entropy within a cryptographic scheme, thus dramatically reducing the computational requirements for obtaining a secret through brute force computation.

Examples of specific side-channel attacks2 that have been well-documented include:

- Simple Power analysis (SPA),
- Simple Electromagnetic Analysis (SEMA),
- Timing Analysis (TA),
- Differential Power Analysis (DPA),
- Differential Electromagnetic Analysis (DEMA),
- Profiling Analysis,
- Differential Collision Analysis (DCA),
- Higher Order Differential Side-Channel Analysis, e.g. second order DPA,
- Multivariate Analysis (Template Attacks),
- Simple Fault Analysis (SFA),
- Differential Fault Analysis (DFA), and
- Stochastic Approach.

In this research, we interpret side channel attacks somewhat more broadly by considering two additional contexts of side channel information: data communications and software execution context. In the former, a side channel attacker may observe patterns in encrypted data communications (e.g., wireless communications) that reveal information about secrets either within the data stream itself or on the communicating device. For example, packet number, packet sizes, transmission timing, or receiver response patterns may prove useful in the cryptographic analysis of a secure communication protocol. Or, it may shed light on the nature and format of a data exchange, for example, identifying sequences of sensitive data within the information stream. Side-channel analysis of the communication channel may also be used to deduce information about device state and cryptographic operations.

The execution context of software running on a SoC device may also be leveraged for a side-channel attack. Context information may include CPU usage metrics, instruction analysis (e.g., branch prediction analysis), cache usage, register analysis, I/O patterns, and so on. By reconstructing a full or partial instruction path of program execution, internal state can be deduced and the entropy protecting data from cryptographic attack significantly reduced.

The term countermeasure is used to describe hardware or software techniques that reduce or eliminate side channel information available to an attacker, thus protecting a system or device against side channel attacks. Example side-channel countermeasures include:

- Structuring cryptographic algorithms to be isochronous across all inputs,
- Use of random timing delays,
- Power line shielding, conditioning, and filtering,
- Randomizing data before execution (blinding),
- Adding random values to sensitive data (masking),
- Introducing noise into side channel information ,
- Reducing statistical correlations, and
- Insuring that an execution path does not depend on secret values (i.e., PC-secure).

While previous work has explored side channel attacks and countermeasures in length, Intel believes there is much more to be done in the design and development of side-channel resistant security specifically for lightweight SoC devices. Such devices are characterized by their:

- Physical exposure to attackers who may have unlimited access to the device,
- Limited computation, memory, and storage resources,
- Limited power resources (following from battery constraints),
- Exposed data communications via wireless communication channels (which are inherently broadcast),
- Frequently sparse patterns of data transfer, and
- Narrowness of device functionality and close coupling with its operating environment.

These and related requirements suggest the need for a distinctly different set of security solutions than widely accepted standards like AES which are too computationally demanding or mismatched with sparse data transfers.

To illustrate, consider a wearable computing device that samples health information periodically and transmits it using wireless communications to an Internet-enabled device (e.g., smart phone) for upload to the cloud. Data transmissions from the device are short yet require privacy. The device itself has limited battery power and is designed to spend a good deal of time in sleep mode. A well-designed security solution might use a lightweight cryptographic scheme matched to the data size and device characteristics. Side-channel information, however, may be used by a knowing attacker to break the cryptographic scheme and understand how instances of the product can be attacked with relatively simple tools and methods. SoC devices in many IoT contexts exhibit similar challenges.

Intel envisions researchers developing security countermeasures and solutions that address the threat of side-channel attacks in such lightweight SoC device applications. As part of such research, Intel hopes to gain a better understanding of the side channel threat, and a better theoretical understanding of what is possible given device constraints. Such understanding will help Intel to construct better semiconductor devices in the future.

1 Evans, D. The Internet of Things: How the Next Evolution of the Internet Is Changing Everything. Cisco Systems. April 2011.

2 Killmann, W., Lange, T., Lochter, M., Thumser, W., and Wicke, G. Minimum Requirements for Evaluating Side-Channel Attack Resistance of Elliptic Curve Implementations. Bundesamt für Sicherheit in der Informationstechnik. January 2011.


The challenge of this research program is to develop novel approaches to security for lightweight SoC devices that protect against side-channel attack. Approaches are expected to be grounded in real-world use cases, yet possess a level of generality that makes it applicable to a broad spectrum of devices.

While researchers may focus on specific attack types, we note that the focus of work should be on solutions making security robust against side-channel attack and not on new techniques for performing side-channel attack. Likewise, researchers may focus on a particular Intel SoC platform for their research effort, but their solutions should not be limited to security surrounding a particular product.

Research proposals in response to this challenge are expected to address one or more of the following three research vectors: RV1: Cryptography, RV2: Data Communications, and RV3: Software. Note that these vectors are not intended to be mutually exclusive. Researchers are free to develop proposals that address any one vector, a combination of two vectors, or even all three vectors simultaneously. In addition, proposals that suggest a compelling topic lying outside these research vectors yet within program objectives and goals are welcome.

RV1: Cryptography. The goal of this research vector is to develop algorithms and technologies that create, adapt, extend, or implement core cryptographic technologies in side-channel resistant manner for lightweight SoC devices. Cryptographic security functions can provide building blocks for a large number of problem-specific solutions in a variety of SoC-based device contexts.

A partial list of relevant topics includes:

  • Block and stream ciphers
  • Symmetric key cryptography
  • Public key cryptography
  • Hash algorithms
  • Digital signatures and message authentication codes

RV2: Data Communications. The goal of this research vector is to develop countermeasures that make SoC-based device communications secure against side-channel attack. Wireless data transmissions, which are broadcast in nature, are arguably vulnerable to would-be attackers by nature. Research in this area looks for opportunities to secure data transfer, despite the inherent broadcast nature of wireless radio transmissions.

A partial list of relevant topics includes:

  • Application of cryptography to communications protocols
  • Approaches to key management
  • Application-level communication protocols
  • Communication within sensor networks
  • Device-to-device communication
  • Client/server communication

RV3: Software. The goal of this research vector is to develop countermeasures and techniques for making SoC software robust against side channel attacks. Solutions should consider the software execution context of the device and the manner in which attackers may use basic hardware state information to attack application-specific secrets.

A partial list of relevant topics includes:

  • Cache management
  • Execution time management
  • Branch prediction logic

Memory last and access patterns

  • Algorithmic masking
  • Fault response and handling logic
  • Operating system support
  • Compiler-based countermeasures

Motivating usage scenarios. While Intel does not wish to constrain SoC-based device usage contexts, proposals should take care to motivate research problems by grounding them in a compelling usage context. In general, a usage model-driven approach to security research should

  1. Identify the SoC-based device usage context under consideration,
  2. Identify key threats and vulnerabilities, and
  3. Propose an approach or framework for protecting against these threats.

Some general usage scenarios were illustrated earlier in the Background section of this CFP. Researchers are encouraged to draw from device usage scenarios with local significance to Brazil; for example, SoC devices associated with DTV media services, transportation/cargo tracking, building energy management systems, and so on.


Intel seeks research projects that are relevant and have the potential high impact within the SoC device solution space. Such projects will clearly address:

  • An important class of side-channel attack either now or in the future, and
  • A security solution or countermeasure demonstrating how resistance to that attack can be achieved.

More specifically, research should address the following goals:

Threat Model

  • Goal 1: Demonstrate the side channel attack and quantify its requirements and complexity. Requirements are demonstrably feasible, making the threat of high importance.

Solution/Countermeasure Robustness

  • Goal 2: Solution or countermeasure increases side-channel attack requirements by 10x-100x or makes it provably infeasible.

Resource Requirements

  • Goal 3: Resources required to implement the solution or countermeasure do not exceed 10-15% of overall device resources, or do not add more than 10-15% resource overhead beyond an existing approach. Resource usage includes:
    • Power requirements
    • CPU, memory, storage
    • Wireless radio usage

Beyond these goals, Intel appreciates approaches that are widely applicable to a variety of SoC device types and usage contexts, those that look more deeply at quantifying the threat of side channel vulnerabilities and those that result in a better theoretical understanding of what is possible given lightweight SoC device constraints.


In order to qualify for this Request for Proposals in the INTEL – FAPESP Agreement, the proponent should satisfy in the following prerequisites:

a) The conditions and restrictions of the FAPESP Program for Cooperative Research for Technological Innovation (PITE) described at are applied here, excluding those restrictions and conditions explicitly excepted in this CFP.

b) The proposals may be submitted by researchers from Higher Education or Research Institutions in the State of São Paulo.

c) Proposals that are incomplete, inaccurate, or are otherwise not responsive to the terms and conditions of this CFP will, at the sole discretion of the Joint Steering Committee for the INTEL-FAPESP cooperation, be excluded from consideration.


Intel and FAPESP contemplate funding a cluster of 2-year grant proposals. Each would be renewable annually contingent upon satisfactory progress and continued promise in research direction.

The total amount available for this CFP is US$ 200,000. FAPESP and Intel reserve the right to propose lower funding levels for projects.

The appropriateness of the requested funding in relation to the proposal goals and qualification of the proposing team is a primary review consideration.


The proposal should clearly state the problems and opportunities to be addressed and the potential impact if the research is successful. It should specifically address the quantifiable goals listed in this request for proposals and provide milestones reflecting the progress towards them.

Please note that Intel and FAPESP are unable to receive proposals that are under an obligation of confidentiality. All proposals submitted should therefore include only public information.

Each proposal must contain the following items (to see the complete checklist of requested documents, please access the submission form, item 16, page7).

FAPESP-INTEL proposal submission form, in Portuguese (form available at

FAPESP CV Summary, in English, for the PI and and co-PIs, including those from Intel, when applicable. Instructions for elaborating CV Summaries are available at

Research team: Listing of all contributing researchers, in English, including Host Institution and Entity. For each one, his or her role in the research project must be defined succinctly, as well as the weekly workload. Each participant must sign his or her agreement to participate in the project. Agreement can be downloaded at

Proposals should be submitted in English and be 12-14 pages in length (not including citations or cost volume), using font Arial size 10 and double spacing. Section 7 is not counted under this page limitation. Please address the sections listed below, from 1 to 6 under separate numbered headings. Each response should comprise the following sections:

  1. Cover page {1 page}. Title of proposal, name(s) of author(s), contact information, name of university, funds requested, the amount of cost share (if any)
  2. Executive summary {1 page}. Define the problem/challenge that this research will address, the effort’s technical objectives/success criteria, and the basic proposed approach.
  3. Relevance and impact claims {1-2 pages}. This section is the centerpiece of the proposal. It should succinctly describe the uniqueness and non-incremental benefits of the proposed objective and approach relative to the state-of-the-art and current approaches.
  4. Detailed technical rationale, approach, and constructive plan {2-4 pages}. Details of proposed research. Proposals should address key issues along one or more of the above research vectors (or another topic still addressing program objectives and goals), and the rationale should include a basis of confidence for meeting the program metrics.
  5. Statement of work, schedule, milestones, success criteria and deliverables {2 pages}. Outline the scope of the effort including tasks to be performed, schedule, milestones, deliverables, and success criteria. It is understood that this is an exploratory research effort and schedules/deliverables reflect intentions rather than a firm commitment.
  6. Proposal team {1-2 pages}. Summarize the members of the program team, their qualifications, and their level of participation in the project.
  7. Other support {1 page}. List other contributions by the Host Institution to this project (cash, goods, or services), if any, but not including items such as the use of university facilities otherwise provided on an ongoing basis. Note that authors of selected proposals will be required to present an original letter on university letterhead signed by the director of the Host Institution certifying the commitment of any additional support.
  8. Fellowships {unlimited}: The proposed budget may include costs for Scientific Initiation, Masters or Post-Doctoral fellowships. The ending dates for each fellowship must happen at or before the ending date of the project. Fellowships can be covered with funds from Intel depending on the analysis of the proposal and the availability of resources, to be verified at the time of selection of proposals. For each requested fellowship a work plan with up to two pages must be submitted together with the research proposal. Work plans must include: Title for the Fellowship research project, Summary, and Description of the plan. It is not necessary to nominate the holder of the fellowship. If the grant is approved, the Principal Investigator will be in charge of organizing a public selection process to select the appointees for the fellowships through a merit review process.
  9. Citations {unlimited}.
  10. Requested budget description {unlimited}. Proposals must include separate budget descriptions for the items requested to FAPESP and to Intel. It is desirable to keep the fraction of the total amount requested for each of the parties at around 50%. Such a balance is desirable but not mandatory, and may deviate from 50% due to specific circumstances to be justified.

a) The budget items that may be requested to FAPESP are those traditionally supported by the Foundation and described in

b) The budget items that can be covered with funds from Intel should be limited to:

  1. i. Resources invested in capital goods or equipment associated with the project if they are donated to the Higher Education and Research Institutions in the State of Sao Paulo;
  2. ii. Resources invested in Scientific Initiation, Masters or Post-Doctoral fellowships with values at least equal to the grants from FAPESP for these fellowships;
  3. iii. Resources invested in consumables and services of third parties when directly associated with the project;
  4. iv. Resources invested in infrastructure associated with the project;
  5. v. Resources for the temporary hiring, during the period of the project, of researchers and technical support staff dedicated to the project in the Host Institution.
  6. vi. Resources for salary complementation of researchers participating in the project employed by the Host Institution;
  7. vii. Special cases documented by a detailed justification within the proposal will be analyzed in each case by the Joint Steering Committee.

c) The budget request must be presented using specific spreadsheets (available at which include:

  1. i. Consolidated Budget Request, classified by types of expense and origin (FAPESP, Intel and other sources);
  2. ii. Separate Budget Request spreadsheets for FAPESP and Intel, by types of expense, following FAPESP’s standards;
  3. iii. Spreadsheets for financial and physical schedule (FAPESP and INTEL).

IMPORTANT: It is necessary to attach three quotes for each capital and equipment expense requested (national or imported). If it is not possible to obtain the 3 quotes requested, please attach a clarification letter.


Proposals should be submitted in a paper copy accompanied by a digital version with a unique PDF file containing the complete proposal.

Proposals that are incomplete, inaccurate, that request funds in excess of the maximum award available, or are otherwise not responsive to the terms and conditions of this CFP will be excluded from consideration.

The envelope containing the proposal should be addressed to:

FAPESP – Fundação de Amparo à Pesquisa do Estado de São Paulo
Rua Pio XI, 1500 - Alto da Lapa
CEP 05468-901 - São Paulo - SP

Proposals will not be accepted by any other means.

Submitted proposals under this CFP will not be returned to the proponents. For record-keeping and administrative purposes, the copy will be archived by FAPESP.

No proposals will be accepted after the closing date for submission, nor will any addendum or explanation be accepted, unless those explicitly and formally requested by FAPESP or Intel.


All received proposals adherent to the terms of this Request for Proposals will be analyzed.

The selection process is based on merit review and comparative analysis. To this end FAPESP will use reviewers' reports and the Foundation’s Area and Supervising Panels.

The criteria used will be that applied to the selection of proposals in the FAPESP Program for Cooperative Research for Technological Innovation (PITE), with the addition of the analysis by the Joint Steering Committee for the FAPESP-INTEL cooperation.

Researchers participating in any submitted proposal will not take part in the analysis and selection process.

The evaluation criteria for this solicitation are as follows:

a) Adherence to the terms of this CFP;

b) Novelty and Ambition of the proposed academic research project, as it relates to the goals of this CFP;

c) Qualification of the research project, in the specification of clear goals, milestones, and success criteria. Clarity of challenges to be overcome and the scientific, technical and material means and ways for this, in relation to the state-of-the-art in the Field, including interface definitions, testing methodology, and plans for experimental deployment;

d) Adequate existing institutional infrastructure, offered by the Host Institution;

e) Qualifications of Principal Investigator and his team, including previous history of work in areas relevant to this CFP, successful completion of previously funded projects, teaching awards, and publications, all of those items being demonstrated in the Curricular Summary of the CV of the Principal Investigator;

f) Ability to complete the project, including the adequacy of available resources, institutional support, reasonableness of timelines, and number and qualifications of identified contributors. Encompasses the efficient use of requested resources and funding, and represent realistic results for the value invested;

g) Potential for wide dissemination and use of intellectual property created, including specific plans for publications, conference presentations, web sites, as well as plans to distribute content in multiple formats or languages;

h) Formation of new researchers and professionals, as a result of the execution of the Project;

i) Potential for technological innovation. The extent to which the proposal’s problem formulation and key approaches are innovative, important, and relevant to the problem at hand. Novelty and ambition of the proposed academic research project, as it relates to the goals of this CFP. Potential for technological innovation as measured by comparisons with existing and competing technologies.

j) Potential contribution and relevance to Intel. The estimated degree to which proposals have a substantial potential for influencing the direction of Intel’s long-range technology plans.




Launching of the CFP at FAPESP Web site


Last date for receiving proposals


Publication of results of the analysis and selection process

From 11/06/2014


The results of the selection process will be announced in FAPESP’s Web Site at and by direct communication to the proponents.


For each research proposal selected, the relationship between FAPESP, Intel and the Principal Investigator Institution will be determined by an agreement defining:

  1. Schedule of disbursements and financial reporting on the amounts disbursed;
  2. Definition and timing of expected results at each stage of the project;
  3. Intellectual property, confidentiality and possible exploitation of project results;
  4. Term;
  5. Legal venue.

The award may be cancelled by Intel and FAPESP by mutual agreement, in the event of justifiable cause, on the basis of evaluation by the Scientific Directors of FAPESP and Intel. Cancellation does not preclude other measures that might be deemed necessary.


If the application is approved, a Grant Contract will be made, which will be signed by the Principal Investigator and the Host Institution´s representative.

The results will be evaluated by progress reports and financial reports that should be submitted on the dates established in the Grant Contract.


By submitting an application under this CFP, applicants confirm that they have read, understood and agreed to the terms and conditions of the CFP and the conditions attached to any successful awards.


All questions related to this CFP must be directed to

Please, put “CFP FAPESP-INTEL” in the subject line of the e-mail to ensure a prompt and proper response. 

Page updated on 11/19/2013 - Published on 11/12/2013